Liquid crystal display (LCD) devices display an image by controlling the light transmittance of liquid crystal using an electric field. Such an LCD device includes an LCD panel having pixel regions arranged in the form of a matrix, and a driving circuit for driving the LCD panel.
In the LCD panel, a plurality of gate lines and a plurality of data lines are arranged such that they cross each other. The pixel regions of the LCD panel are arranged at regions defined by the crossing gate lines and data lines. Pixel electrodes and a common electrode are formed in the liquid crystal panel, to apply an electric field to each pixel region.
Each pixel electrode is connected to an associated one of the data lines via source and drain electrodes of a thin film transistor (TFT) which functions as a switching element. The TFT is turned on by a scan pulse applied to the gate electrode of the TFT via the associated gate line, to enable the pixel electrode to be charged with a data signal from the associated data line.
The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for supplying control signals for control of the gate driver and data driver, and a power supply for supplying various drive voltages used in the LCD device.
The timing controller controls drive timings of the gate driver and data driver, and supplies a pixel data signal to the data driver. The power supply boosts or reduces an input voltage, to generate drive voltages such as a common voltage VCOM, a gate-high-voltage signal VGH, and a gate-low-voltage signal VGL. The gate driver sequentially supplies scan pulses to the gate lines, to enable liquid crystal cells of the LCD panel to be sequentially driven on a line-by-line basis. The data driver supplies a pixel voltage signal to each data line every time a scan pulse is supplied to one of the gate lines. In this manner, the LCD device displays an image by controlling the light transmittance of each liquid crystal cell by an electric field applied between the associated pixel electrode and the common electrode in accordance with a pixel voltage signal applied to the data line associated with the liquid crystal cell.
In order to sequentially output scan pulses, the gate driver includes a shift register such as is shown in FIG. 1. The shift register includes n stages AST1 to ASTn and one dummy stage ASTn+1 which are connected in series. The stages AST1 to ASTn+1 output scan pulses Vout1 to Voutn+1, respectively. That is, the scan pulses Vout1 to Voutn+1 are output in a sequential manner from the stages AST1 to ASTn+1, starting from the first stage AST1, and ending at the dummy stage ASTn+1. The scan pulses Vout1 to Voutn output from the stages AST1 to ASTn, except for the dummy stage ASTn+1, are sequentially supplied to gate lines of a liquid crystal panel (not shown), respectively, to cause the gate lines to be sequentially scanned.
Each of the stages AST1 to ASTn+1 of the shift register receives a first voltage VDD, a second voltage VSS, and two of first through fourth clock pulses CLK1 to CLK4. Successive clock pulses of the first through fourth clock pulses CLK1 to CLK4 have a phase difference from each other. The first voltage VDD is a positive voltage, whereas the second voltage VSS is a ground voltage.
The first stage AST1, which is arranged upstream from the remaining stages AST1 to ASTn+1, receives a start pulse SP, in addition to the first voltage VDD, second voltage VSS, and two clock pulses.
In an LCD device having an increased display area, gate lines thereof have an increased length. As the length of the gate lines increases, the resistance and capacitance components of the gate lines are increased. Scan pulses supplied to the gate lines may be distorted by the increased resistance and capacitance components. In FIG. 2, shows an ideal scan pulse 201 where it is assumed that there are no resistance and capacitance components in the associated gate line. On the other hand, resistance and capacitance components of the associated gate line increase the rise time TR of the scan pulse resulting in a distorted pulse 202, Since the distorted scan pulse 202 has an increased rise time TR, as compared to the ideal scan pulse 201, the effective charging time TS, for which the scan pulse is maintained at a target voltage VT, is shortened. When the scan pulse 202, which has a distorted waveform, as mentioned above, is applied to the gate electrode of the associated TFT, the turn-on time of the TFT is reduced, thereby reducing the time duration of the data voltage supplied from the associated data line by the turned-on TFT. As a result, the waveform of the data voltage applied to the associated pixel electrode via the drain/source terminal of the turned-on TFT is distorted, and the data voltage is insufficiently charged in the pixel electrode.